Numerical Problems with Pipelining
Q6: Consider a non-pipelined processor with a clock rate of 2.5 gigahertz
and average cycles per instruction of 4. The same processor is upgraded to a
pipelined processor with five stages but due to the internal pipeline delay,
the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the
pipeline. The speed up achieved in this pipelined processor is-
1. 3.2
2. 3.0
3. 2.2
4. 2.0
Solution-
Cycle Time in
Non-Pipelined Processor-
Frequency
of the clock = 2.5 gigahertz
Cycle time
= 1 /
frequency
= 1 / (2.5
gigahertz)
= 1 / (2.5
x 109 hertz)
= 0.4 ns
Non-Pipeline
Execution Time-
Non-pipeline
execution time to process 1 instruction
= Number
of clock cycles taken to execute one instruction
= 4 clock
cycles
= 4 x 0.4
ns
= 1.6 ns
Cycle Time in
Pipelined Processor-
Frequency
of the clock = 2 gigahertz
Cycle time
= 1 / frequency
= 1 / (2
gigahertz)
= 1 / (2 x
109 hertz)
= 0.5 ns
Pipeline
Execution Time-
Since
there are no stalls in the pipeline, so ideally one instruction is executed per
clock cycle. So,
Pipeline
execution time
= 1 clock
cycle
= 0.5 ns
Speed Up-
Speed up
=
Non-pipeline execution time / Pipeline execution time
= 1.6 ns /
0.5 ns
= 3.2
Thus, Option (A) is correct.
Q7: The stage delays in a 4-stage pipeline are 800, 500, 400 and 300
picoseconds. The first stage is replaced with a functionally equivalent design
involving two stages with respective delays 600 and 350 picoseconds.
The
throughput increase of the pipeline is _____%.
Solution-
Execution Time in
4 Stage Pipeline-
Cycle time
= Maximum
delay due to any stage + Delay due to its register
= Max {800,
500, 400, 300} + 0
= 800
picoseconds
Thus,
Execution time in 4 stage pipeline = 1 clock cycle = 800 picoseconds.
Throughput in 4
Stage Pipeline-
Throughput
= Number
of instructions executed per unit time
= 1
instruction / 800 picoseconds
Execution Time in
2 Stage Pipeline-
Cycle time
= Maximum
delay due to any stage + Delay due to its register
= Max {
600, 350 } + 0
= 600
picoseconds
Thus,
Execution time in 2 stage pipeline = 1 clock cycle = 600 picoseconds.
Throughput in 2
Stage Pipeline-
Throughput
= Number
of instructions executed per unit time
= 1
instruction / 600 picoseconds
Throughput
Increase-
Throughput
increase
= { (Final
throughput – Initial throughput) / Initial throughput } x 100
= { (1 /
600 – 1 / 800) / (1 / 800) } x 100
= { (800 /
600) – 1 } x 100
= (1.33 –
1) x 100
= 0.3333
x 100
= 33.33 %
Q8: A non-pipelined single cycle processor
operating at 100 MHz is converted into a synchronous pipelined processor with
five stages requiring 2.5 ns, 1.5 ns, 2 ns, 1.5 ns and 2.5 ns respectively. The
delay of the latches is 0.5 sec.
The speed up of the pipeline processor for a large number
of instructions is-
1. 4.5
2. 4.0
3. 3.33
4. 3.0
Solution-
Cycle Time in Non-Pipelined
Processor-
Frequency of the clock = 100 MHz
Cycle time
= 1 / frequency
= 1 / (100 MHz)
= 1 / (100 x 106 hertz)
= 0.01 μs
Non-Pipeline Execution Time-
Non-pipeline execution time to process 1
instruction
= Number of clock cycles taken to execute
one instruction
= 1 clock cycle
= 0.01 μs
= 10 ns
Cycle Time in Pipelined
Processor-
Cycle time
= Maximum delay due to any stage + Delay
due to its register
= Max {2.5, 1.5, 2, 1.5, 2.5} + 0.5 ns
= 2.5 ns + 0.5 ns
= 3 ns
Pipeline
Execution Time-
Pipeline
execution time
= 1 clock
cycle
= 3 ns
Speed Up-
Speed up
=
Non-pipeline execution time / Pipeline execution time
= 10 ns /
3 ns
= 3.33
Thus,
Option (C) is correct.
Q9: We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 has 5 stage pipelines with execution time of 3 ns, 2 ns, 4 ns, 2 ns and 3 ns. While the design D2 has 8 pipeline stages each with 2 ns execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions?
1. 214 ns
2. 202 ns
3. 86 ns
4. 200 ns
Solution-
Cycle Time in Design
D1-
Cycle time
= Maximum
delay due to any stage + Delay due to its register
= Max {3,
2, 4, 2, 3} + 0
= 4 ns
Execution Time For 100 Instructions in Design D1-
Execution
time for 100 instructions
= Time
taken for 1st instruction + Time taken for remaining 99 instructions
= 1 x 5
clock cycles + 99 x 1 clock cycle
= 5 x
cycle time + 99 x cycle time
= 5 x 4 ns
+ 99 x 4 ns
= 20 ns +
396 ns
= 416 ns
Cycle Time in Design D2-
Cycle time
= Delay
due to a stage + Delay due to its register
= 2 ns + 0
= 2 ns
Execution Time For 100 Instructions in Design D2-
Execution
time for 100 instructions
= Time
taken for 1st instruction + Time taken for remaining 99 instructions
= 1 x 8
clock cycles + 99 x 1 clock cycle
= 8 x
cycle time + 99 x cycle time
= 8 x 2 ns
+ 99 x 2 ns
= 16 ns +
198 ns
= 214 ns
Time Saved-
Time saved
=
Execution time in design D1 – Execution time in design D2
= 416 ns –
214 ns
= 202 ns
Thus,
Option (B) is correct.
Q-10: Consider an instruction pipeline with four stages (S1, S2, S3 and S4)
each with combinational circuit only. The pipeline registers are required
between each stage and at the end of the last stage. Delays for the stages and
for the pipeline registers are as given in the figure-
What is the
approximate speed up of the pipeline in steady state under ideal conditions
when compared to the corresponding non-pipeline implementation?
- 4.0
- 2.5
- 1.1
- 3.0
Solution-
Non-Pipeline Execution Time-
Non-pipeline
execution time for 1 instruction
= 5 ns + 6 ns
+ 11 ns + 8 ns
= 30 ns
Cycle
Time in Pipelined Processor-
Cycle time
= Maximum
delay due to any stage + Delay due to its register
= Max {5, 6,
11, 8} + 1 ns
= 11 ns + 1 ns
= 12 ns
Pipeline
Execution Time-
Pipeline
execution time
= 1 clock cycle
= 12 ns
Speed Up-
Speed up
= Non-pipeline
execution time / Pipeline execution time
= 30 ns / 12
ns
= 2.5
Thus, Option
(B) is correct.
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