Computer Architecture Previous Questions Bank (COA)

Computer Architecture Previous Questions Bank (COA) 

Supplement/Improvement Examination: Jan -2025

1.	a)	Explain the necessity of pipeline in Computer Architecture.	[4]
	b)	How does pipelining improve CPU performance?	[4]
	c)	Explain behind the concept of Structural hazards in pipelined architectures.	[6]
2.	a)	Mention five Cache Replacement Policies name.	[4]
	b)	Explain the advantage and disadvantage of Direct cache mapping.	[5]
	c)	Consider a fully associative cache memory with 4 lines that implements LIFO cache replacement policy. For the following block request- 2,3,4,7,6,3,4,7,5,4,7,8. What is Miss and Hit ratio respectively?	[5]
3.	a)	Explain 3C’s in Cache mapping.	[4]
	b)	Explain behind the concept of Associative Mapping in Cache with appropriate figure.	[5]
	c)	Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 512 KB. Find out the number of bits in tag and tag directory size.	[5]
4.	a)	Differentiate between EPROM and EEPROM.	[4]
	b)	Describe different levels of Cache Memory.	[4]
	c)	Explain how cache written policy works in system with appropriate figure.	[6]
5.	a)	Mention some names of Secondary memory.	[2]
	b)	Define term- SRAM, DRAM and Virtual memory.	[2×3=6]
	c)	Briefly describe the necessity of memory hierarchy in the system.	[6]
6.	a)	Define Flynn’s taxonomy in Computer Architecture.	[4]
	b)	Explain how does cache mapping affect the cache hit rate, and what factors influence it.	[4]
	c)	Comparison among Direct Mapping vs Associative Mapping vs K way Associative Mapping.	[6]
7.	a)	Make short note on “locality of Reference in Cache”.	[4]
	b)	Explain different types of Cache Access with appropriate figure.	[5]
	c)	Assume that for a certain processor, a read request takes 50 ns on a cache miss and 6 ns on a cache hit. Suppose while running a program, it was observed that 60% of the processor's read requests result in a cache hit. The average read access time in ns is?	[5]

 Semester Final Examination, October-2023(Held in April-2024)

1.	a)	Define term: Memory Address Register, Memory Buffer Register.	[2+2]
	b)	Differentiate between Computer Architecture and Computer Organization.	[4]
	c)	Explain the scenario of relationship between ISA and HSA with appropriate figure in Computer Architecture.	[6]
2.	a)	Illustrate term Memory Interfacing.	[3]
	b)	Distinguish between Von Neumann and Non von Neumann Architecture.	[4]
	c)	Explain Flynn's classification of Computer with appropriate figure.	[6]
3.	a)	Why Memory Hierarchy is required in the system?	[2]
	b)	Differentiate among Register, Cache, Primary memory and Secondary memory.	[5]
	c)	Explain Cache written policy with appropriate figure.	[7]
4.	a)	Define term “Cache Hit” and “Cache Miss”.	[2]
	b)	Assume that for a certain processor, a read request takes 40 nanoseconds on a cache miss and 7 nanoseconds on a cache hit. Suppose while running a program, it was observed that 70% of the processors read requests result in a cache hit. Find out the average read access time?	[5]
	c)	Describe Simultaneous and Hierarchical Cache Accesses with appropriate figure	[7]
5.	a)	Explain locality of Reference in Cache.	[3]
	b)	Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find out the number of bits in tag and tag directory size.	[2.5+2.5]
	c)	Explain how does direct cache mapping work, and what is its primary advantage?	[6]
6.	a)	Define the term "conflict miss" and discuss how it relates to cache mapping techniques.	[4]
	b)	How does pipelining improve CPU performance?	[4]
	c)	How do data hazards occur in a pipelined processor, and what techniques are used to mitigate them?	[6]
7.	a)	Briefly explain K-way set associative mapping in computer architecture.	[4]
	b)	Differentiate between Software and Hardware interrupt with example.	[4]
	c)	How are cache mapping techniques implemented in modern computer architectures, considering factors like multi-core processors and hierarchical cache designs?	[6]

Semester Final Examination: April -2024(Held in October -2024)

1.	a)	Briefly describe the necessity of memory hierarchy in the system.	[4]
	b)	“Virtual Memory works as a RAM sometimes”- Justify the comment.	[4]
	c)	Extrapolate the scenario of relationship between ISA and HSA in computer architecture.	[6]
2.	a)	Define term- SRAM, DRAM, EPROM and EEPROM.	[1×4]
	b)	Discuss locality of Reference in Cache.	[5]
	c)	Explain how cache written policy works in system with appropriate figure.	[5]
3.	a)	Make short note on “locality of Reference in Cache”.	[4]
	b)	Explain Simultaneous and Hierarchical Cache Accesses with appropriate figure.	[5]
	c)	Assume that for a certain processor, a read request takes 40 ns on a cache miss and 4 ns on a cache hit. Suppose while running a program, it was observed that 70% of the processor's read requests result in a cache hit. The average read access time in ns is?	[5]
4.	a)	Briefly describe different levels of Cache Memory.	[3]
	b)	Explain how does cache mapping affect the cache hit rate, and what factors influence it.	[5]
	c)	Comparison among Direct Mapping vs Associative Mapping vs K way Associative Mapping.	[6]
5.	a)	Illustrate term- Conflict Miss, Compulsory Miss and Capacity Miss	[1×3]
	b)	Explain behind the concept of Direct Mapping in Cache with appropriate figure.	[5]
	c)	Consider a direct mapped cache of size 32 KB with block size 512 bytes. The size of main memory is 256 KB. Find out the number of bits in tag and tag directory size.	[6]
6.	a)	Mention five Cache Replacement Policies name.	[4]
	b)	Explain the advantage and disadvantage of fully associative cache mapping.	[4]
	c)	Consider a fully associative cache memory with 4 lines that implements FIFO cache replacement policy. For the following block request- 2,3,4,7,6,3,4,7,5,4,7,8. What is Miss and Hit ratio respectively?	[6]
7.	a)	Mention different types of pipeline hazard.	[2]
	b)	How does pipelining improve CPU performance?	[5]
	c)	Explain behind the concept of control hazards in pipelined architectures.	[7]

Semester Final Examination, April - 2022

1.	a.	What do you understand by computer architecture? Explain the System Bus model of a computer system with figure.	[1+3]
	b.	Write short notes on i) I/O channel ii) Data bus	[2+2]
	c.	Describe memory hierarchy of computer system with figure.	[6]
2.	a.	What do you mean by ALU? Design 32-bit ALU using 1-bit ALUs.	[1+3]
	b.	Describe the classification of instruction set of a processor.	[4]
	c.	Define virtual memory in computer. Discuss the working process of virtual memory with figure.	[1+5]
3.	a.	What is datapath? Explain register file for R-format instructions.	[1+3]
	b.	Sketch a datapath for R-format instructions and mention the datapath steps.	[6]
	c.	Write some differences between single cycle and multi cycle datapath.	[4]
4.	a.	What is pipelining? Explain the hardware organization of four stage instruction pipeline with figure.	[1+5]
	b.	Define processor pipelining. What is the difference between static and dynamic   pipelining?	[2+2]
	c.	Write some differences between pipelining and non-pipelining.	[4]
5.	a.	What do you understand by data hazards? Explain the situations in which a data hazard can occur.	[2+6]
	b.	Which is the fastest computer memory? Explain it.	[3]
	c.	Write some advantages and disadvantages of virtual memory.	[3]
6.	a.	What is DMA? Explain the working principle of DMA with figure.	[1+5]
	b.	Write a short note on modes of DMA.	[4]
	c.	Compare RISC and CISC processor.	[4]
7.	a.	Convert a floating point number 72.25 into single and double precision format.	[7]
	b.	Define CPU time, CPI and MIPS.	[3]
	c.	What are the differences between hardwired control unit and microprogrammed control unit?	[4]

Semester Final Examination, April - 2023

1.	a.	What do you mean by computer architecture? With a diagram, explain the Von Neumann model of a digital computer.	[1+5]
	b.	Draw the memory hierarchy of a computer and explain auxiliary memory.	[5]
	c.	Distinguish between data bus and address bus.	[3]
2.	a.	What do you understand by DMA? Describe the block diagram of DMA.	[1+5]
	b.	Define ALU. Design 4-bit ALU using 4:1 multiplexer.	[1+3]
	c.	Explain any two modes of DMA.	[4]
3.	a.	State pipelining and describe 4-stage instruction pipelining.	[6]
	b.	Point out differences between pipelining and non- pipelining system.	[4]
	c.	Mention the types of pipelining and define any two.	[4]
4.	a.	Explain the general steps taken to execute a program with figure.	[4]
	b.	Compare single cycle and multi cycle datapath.	[3]
	c.	Sketch the datapath for R-format instructions and explain the datapath steps.	[7]
5.	a.	Define data hazard and explain three situations in which a data hazard can occur.	[8]
	b.	Make a brief note about Input Output channel.	[3]
	c.	Classify I/O channel and briefly explain.	[3]
6.	a.	Define- i) CPU execution time  ii) MIPS    iii) Throughput  iv) Response time	[4]
	b.	A program of 1500 instructions run 2min on machine with 90Hz clock. Find out the CPI.	[3]
	c.	Convert a floating point number -62.125 into single and double precision format.	[7]
7.	a.	How does virtual memory work?	[7]
	b.	Indicate some limitations of virtual memory.	[3]
	c.	Define cache memory. Briefly explain the performance of cache memory.	[1+3]

Semester Final Examination, Oct - 2023

1.	a)	Define computer architecture. Discuss the necessity of computer architecture in Computer Science & Engineering sector.	[1+4]
	b)	Why do we need system bus? Explain system bus model with figure.	[2+5]
	c)	Point out the basic difference between Von Neumann model and System Bus model.	[2]
2.	a)	What do you understand by instructions? Classify and explain the types of instructions.	[1+4]
	b)	Write short notes on- i. Virtual memory ii. I/O channel   iii. CPU execution time	[3x2]
	c)	Construct 32-bit ALU by using 1-bit ALUs.	[3]
3.	a)	State DMA controller. Analyze the working process of DMA controller with figure.	[1+5]
	b)	Indicate the modes of DMA and define any two of them.	[3]
	c)	Design and explain Hardwired Control Unit briefly.	[5]
4.	a)	How do you differentiate between datapath and single cycle datapath? List out the datapath elements and state.	[2+3]
	b)	Make a brief note about multi-cycle datapath.	[3]
	c)	Consider a R-format instruction and explain the datapath steps of it.	[6]
5.	a)	Define pipelining and discuss 5-stage instruction pipelining shortly.	[7]
	b)	Briefly explain any two situations in which a data hazard can occur.	[4]
	c)	State any three types of pipelining.	[3]
6.	a)	Describe the types of multi-processor with figure.	[5]
	b)	Write three applications of multi-processor.	[3]
	c)	How does the structural hazard happen?	[3]
	d)	Write a short note on non- pipelining system.	[3]
7.	a)	Define cache memory. When do cache hit and cache miss happen?	[1+2]
	b)	What do you understand by MMU, page offset and page table in case of virtual memory management technique?	[3]
	c)	Take a floating-point number and represent it into single and double precision format.	[8]