Instruction Pipelining | Performance in Computer Architecture
In instruction pipelining,
1) A form of parallelism
called as instruction level parallelism is implemented.
2) Multiple instructions
execute simultaneously.
3) The efficiency of pipelined
execution is more than that of non-pipelined execution.
Performance of Pipelined Execution-
The following parameters serve as criterion to estimate the performance of pipelined execution -
1) Speed Up
2) Efficiency
3) Throughput
1. Speed Up -
It gives
an idea of “how much faster” the
pipelined execution is as compared to non-pipelined
execution.
It is calculated as -
2. Efficiency -
The
efficiency of pipelined execution is calculated as -
3. Throughput -
Throughput
is defined as number of instructions executed per unit time.
It is
calculated as -
Calculation of Important Parameters-
Let us
learn how to calculate certain important parameters of pipelined architecture.
Consider-
1) A pipelined architecture consisting of k-stage pipeline
2) Total number of instructions to be executed = n
Point-01: Calculating Cycle Time-
In
pipelined architecture,
1) There is a global clock that synchronizes the working of
all the stages.
2) Frequency of the clock is set such that all the stages
are synchronized.
3) At the beginning of each clock cycle, each stage reads
the data from its register and process it.
4) Cycle time is the value of one clock cycle.
There are
two cases possible-
Case-01: All the stages offer same delay-
If all the
stages offer same delay, then-
Cycle time = Delay offered by one stage including the delay due to its register
Case-02: All the stages do not offer same delay-
If all the
stages do not offer same delay, then-
Cycle time = Maximum delay offered by any
stage including the delay due to its register
Point-02: Calculating Frequency of Clock-
Frequency of the clock (f) = 1 / Cycle time
Point-03: Calculating Non-Pipelined Execution Time-
In non-pipelined architecture,
· The instructions execute
one after the other.
· The execution of a new
instruction begins only after the previous instruction has executed completely.
· So, number of clock cycles
taken by each instruction = k clock cycles
Thus,
Non-pipelined
execution time
= Total
number of instructions x Time taken to execute one instruction
= n x k clock cycles
Point-04: Calculating Pipelined Execution Time-
In
pipelined architecture,
1) Multiple instructions execute parallelly.
2) Number of clock cycles taken by the first instruction = k
clock cycles
3) After first instruction has completely executed, one
instruction comes out per clock cycle.
4) So, number of clock cycles taken by each remaining
instruction = 1 clock cycle
Thus,
Pipelined
execution time
= Time
taken to execute first instruction + Time taken to execute remaining
instructions
= 1 x k
clock cycles + (n-1) x 1 clock cycle
= (k + n –
1) clock cycles
Point-04: Calculating Speed Up-
Speed up
=
Non-pipelined execution time / Pipelined execution time
= n x
k clock cycles / (k + n – 1) clock cycles
= n x
k / (k + n – 1)
= n x k /
n + (k – 1)
= k / {1 +
(k – 1)/n}
1) For very large number of instructions, n→∞. Thus, speed
up = k.
2) Practically, total number of instructions never tend to
infinity.
3) Therefore, speed up is always less than number of stages
in pipeline.
Important Notes-
Note-01:
1) The aim of pipelined architecture is to execute one
complete instruction in one clock cycle.
2) In other words, the aim of pipelining is to maintain
CPI ≅ 1. Practically, it is not possible to achieve CPI ≅ 1 due to delays that get introduced due to
registers.
3) Ideally, a pipelined architecture executes one complete
instruction per clock cycle (CPI=1).
Note-02:
1) The maximum speed up that can be achieved is always equal
to the number of stages.
2) This is achieved when efficiency becomes 100%.
3) Practically, efficiency is always less than 100%.
4)
Therefore, speed up is
always less than number of stages in pipelined architecture.
Note-03:
Under
ideal conditions,
1) One complete instruction is executed per clock cycle i.e.
CPI = 1.
2) Speed up = Number of stages in pipelined architecture
Note-04:
1) Experiments show that 5 stage pipelined processor gives
the best performance.
Note-05:
In case
only one instruction has to be executed, then-
1) Non-pipelined execution gives better performance than
pipelined execution.
2) This is because delays are introduced due to registers in
pipelined architecture.
3) Thus, time taken to execute one instruction in
non-pipelined architecture is less.
Note-06:
High
efficiency of pipelined processor is achieved when-
1) All the stages are of equal duration.
2) There are no conditional branch instructions.
3) There are no interrupts.
4) There are no register and memory conflicts.
5) Performance degrades
in absence of these conditions.
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