Lecture-12: Interrupt in Microprocessor (MPU)

Interrupt in Microprocessor

"An interrupt is a mechanism by which an external device or software gets the attention of the microprocessor to perform a specific task urgently."

Interrupts in 8086 Microprocessor are signals that temporarily halt the current program execution and force the CPU to execute a special routine called ISR (Interrupt Service Routine). After the ISR completes, the CPU resumes the original program from where it left off.

 

   Interrupt Handling Sequence (INTR):

1.    Interrupt Request → External device asserts INTR.

2.    CPU Checks → At end of current instruction, if IF=1, CPU responds.

3.    INTA Pulse 1 → 8086 asserts INTA; PIC prepares vector.

4.    INTA Pulse 2 → PIC places Type Number on data bus.

5.    Save Context → CPU pushes FLAGS, CS, IP onto stack.

6.    Fetch Vector → CPU computes address: Type × 4 → reads new IP & CS.

7.    Jump to ISR → Execution starts at new CS:IP.

8.    IRET → At end of ISR: Pop IP, CS, FLAGS → return.

Interrupt are classified into following groups based on their parameter –

🔹 Software Interrupts

1)      These are generated by instructions written in the program.

2)      The INT instruction is used to invoke a software interrupt (e.g., INT 21H).

3)      They are mainly used for system calls, I/O operations, or invoking DOS functions.

4)      The interrupt type number is specified in the instruction (0–255).

Example:

INT 21H; Call DOS function

In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.

 

🔹 Hardware Interrupts

1)    These are generated by external devices to get the CPU’s attention.

2)    The 8086 has two hardware interrupt pins:

a. INTR (Interrupt Request): Maskable interrupt (can be enabled/disabled using IF flag).

b.    NMI (Non-Maskable Interrupt): Non-maskable; cannot be disabled, used for urgent events like power failure.

3)    The CPU stops current execution and jumps to the interrupt service routine (ISR) address.

There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5,  RST6.5, RST5.5, INTA.

⚖️ Difference Between Software and Hardware Interrupts:

Feature	Software Interrupt	Hardware Interrupt
Source	Generated by program instructions	Generated by external hardware devices
Example	INT 21H, INT 10H	INTR, NMI
Control	Programmer-controlled	Controlled by hardware
Masking	Cannot be masked	INTR can be masked, NMI cannot
Instruction Involved	Uses INT instruction	Triggered by electrical signal on interrupt pins
Usage	System calls, debugging, predefined services	Keyboard input, I/O device request, emergency signals

Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR.

Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5.

Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP.

Interrupt Service Routine (ISR)- A small program or a routine that when executed, services the corresponding interrupting source is called an ISR.

TRAP- It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers the control to the location 0024H.

RST7.5- It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH address.

 

RST 6.5 - It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H address.

RST 5.5- It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH address.

INTR- It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor.

 

How does Interrupt work?

EI= Enable Interrupt.

1. Using Interrupt EI (Enable Interrupt) instruction set the EI Flip-Flop.

2. If EI is set, processor execute an instruction & check the INTR.

3. If EI is sent & INTR is high processor, received interrupt request.

4. Once processor receive the request it sends INTR (active low) signal to external. Hardware.

5. Processor read the Interrupt from External Hardware.

6. Processor push the returning address (PC) into stack and load the base address of the ISR into PC program center (PC) switches to ISR as well as the program contains.

7. If executes the ISR (Interrupt Service Routine) before executing RET instruction. It set the interrupt enable Flip-Flop then executed RET instructions.

8. Once the RET instructions execute, it pops returning address and load it to PC (program center). Then automatically PC re-indicates the program executions.